1. Technical Field
The present invention relates to a method and system for utilizing system memories in general and, in particular, to a method and system for utilizing system memories within a symmetric multiprocessor data-processing system. Still more particularly, the present invention relates to a method and system for increasing system memory bandwidth within a symmetric multiprocessor data-processing system.
2. Description of the Prior Art
The performance of a system memory in a data-processing system depends on both latency and bandwidth. In a conventional uniprocessor data-processing system, the latency of a system memory is generally more important to the efficient operation of cache memories while the bandwidth of the system memory is generally more important to the efficient operation of I/O components. However, as the number/size of cache memories increases, the bandwidth of the system memory becomes important to the cache memories also. Especially in a symmetric multiprocessor (SMP) data-processing system in which the number/size of the cache memory is much higher than the conventional uniprocessor data-processing system, the bandwidth of the system memory has a more direct impact on the performance of the cache memories, which will subsequently affect the overall system performance.
An SMP data-processing system has multiple processing units that are generally identical. In other words, these processing units have the same architecture and utilize a common set or subset of instructions and protocols to operate. Typically, each processing unit includes a processor core having at least one execution unit for carrying out program instructions. In addition, each processing unit may include at least one level of caches, commonly referred to as L1 or primary caches, which are implemented with high-speed memories. In most cases, a second level of caches, commonly referred to as L2 or secondary caches, may also be included in each processing unit for supporting the first level caches. Sometimes, a third level of caches, commonly referred to as L3 or tertiary caches, may also be included in each processing unit for supporting the second level caches. Each level of cache stores a subset of the data and instructions contained in the system memory for low latency access by the processor cores.
Often, these caches have a data width of two to four words in order to match the access bandwidth of the processor cores. Similarly, the system memory is also two to four words wide in order to match the width of the caches. Hence, the bandwidth of the system memory can easily be doubled or quadrupled by simply doubling or quadrupling the width of the system memory. However, additional hardware is required for the multiplexing between the caches and the system memory, which may lead to additional cost and lower system performance. The present invention provides an improved method for increasing the bandwidth of a system memory within a SMP data-processing system without resorting to increasing the data width of the system memory.